The present invention generally relates to error suppression systems, and more particularly to an error suppression system for suppressing a spread of an error generated in differential coding in which a phase of a carrier is relatively shifted depending on each bit of transmission data.
Conventionally, in a digital radio multiplex communication system, no phase information of the carrier is transmitted when transmitting data. For this reason, a receiving terminal may synchronize to one or a plurality of phases. In the case of a 2-phase phase shift keying (PSK), for example, it is uncertain on the receiving terminal end whether the synchronization phase is "0" or ".pi.".
Accordingly, a differential coding is employed in the digital radio multiplex communication system. According to the differential coding, a transmitting end modulates the transmission data depending on a phase difference of the carrier and a receiving end reproduces the transmission data independently of the absolute phase of the carrier. As a result, even when the synchronization phase is different from the absolute phase of the carrier, the receiving end does not require an operation which is dependent on the synchronization phase such as inverting the polarity and switching the channels.
A description will be given of a conventional differential coding circuit for the case where the 2-phase PSK is employed. FIG. 1 shows an example of a conventional differential coding circuit, and FIG. 2 shows an example of a conventional differential decoding circuit. FIG. 3 shows output logic values at various parts of the differential coding and decoding circuits shown in FIGS. 1 and 2. In FIG. 3, a rectangular mark indicates a frame bit inserting position and a frame bit, a circular mark indicates an error bit, an underline indicates a presumed value, and a "x" mark indicates an uncertain logic value.
At the transmitting terminal, a frame bit inserting circuit 71 shown in FIG. 1 inserts a predetermined frame bit into the transmission data the speed of which is already converted into a predetermined bit rate. An exclusive-OR gate 72 obtains an exclusive-OR of an output of the frame bit inserting circuit 71 and an output of a flip-flop 73 so as to carry out a sum logic conversion. The output of the flip-flop 73 is supplied to a modulator (not shown) as an output of the differential coding circuit.
At the receiving terminal, an exclusive-0R gate 82 shown in FIG. 2 obtains an exclusive-OR of an output of a flip-flop 81 and consecutive bits output from a demodulator (not shown) so as to carry out a difference logic conversion. In other words, the transmission data is decoded. A frame synchronizing circuit 83 detects the frame bit from the decoded data and carries out a frame synchronization. An output of the exclusive-OR gate 82 is supplied to a speed conversion part or the like.
According to the differential coding using the difference logic, a 1-bit error which is generated in a transmission path spreads to consecutive bits by the decoding. FIG. 4 shows the spread of the bit error. In FIG. 4, the same designations are used as in FIG. 3.
An error bit A is output via the exclusive-0R gate 82 as a bit B having an erroneous logic value and is held as it is in the flip-flop 81. Accordingly, at a timing which is delayed by one bit, a bit C which is held by the flip-flop 81 has an erroneous logic value, and as a result, a bit D which is output from the exclusive-OR gate 82 also has an erroneous logic value.
In addition, in a system which employs an error correction code, it is necessary to add redundant bits to the transmission data. However, there is a limit to the occupied bandwidth, and there is accordingly a limit to the number of redundant bits which may be added. Therefore, although the error inevitably which spreads to the consecutive bits in the differential coding, there is a problem in that it is extremely difficult to correct the error spread in the consecutive bits.